In an article in Nature Electronics, the researchers describe the new so-called 1T1R configuration, in which a memory cell is integrated with a vertical transistor selector, all in nano-size. This brings improvements in scalability, speed, and energy efficiency compared to current mass storage solutions.
The basic issue is that things that require handling large amounts of data, such as AI and machine learning, need increasingly larger and faster capacities. For this to be successful, the memory and the processor doing the calculations need to be as close together as possible. In addition, computations need to be performed in an energy-efficient way, especially as today’s technology generates high temperatures at high loads.
Bottleneck
The problem of processors performing calculations much faster than the speed of memory has been well known for many years. In technical language, it is called the “von Neumann bottleneck”, and is caused by the fact that the memory and computing devices are separate and it takes time to send information back and forth over a so-called bus, which limits the speed.
“Processors have evolved rapidly over many years. On the memory side, storage capacity has increased steadily, but functionality has been rather stagnant,” says Saketh Ram Mamidala, a doctoral student in nanoelectronics at LTH and one of the authors of the paper.
“Works surprisingly well”
Traditionally, the limitation has been to build circuit boards where the devices lie next to each other on a flat surface. The idea now is to build vertically in a 3D configuration and integrate memory and processor, with the calculations taking place inside the memory circuit itself.
“Our version is a nanowire with a transistor at the bottom and a very small memory element sitting on top of the same wire. This makes it a compact integrated function where the transistor controls the memory element. The idea has been around before, but performance has been hard to come by. But we are now showing that it can be done and that it works surprisingly well,” says Lars-Erik Wernersson, professor of nanoelectronics.
The memory cell the researchers are working with is RRAM (Resistive Random-Access Memory) and is not new in itself, but what is new is how they managed to make a functional integration that creates great opportunities. This opens up new fields of research and new and improved functions in everything from AI and machine learning to, in the long term, ordinary computers. Future applications could include various forms of machine learning such as radar-guided gesture control, climate modeling, or the development of various medicines.
“The memory works even without a power supply,” says Saketh Ram Mamidala.
Unique material integration
Lund University, with the Center for Nanoscience and the Faculty of Engineering, has for a long time been successful in building nanowires within the so-called III-V technology platform. The material integration available in Lund is unique and has benefited greatly from the MAX IV laboratory to develop the material and understand its chemical properties.
“It is certainly possible to find solutions in silicon too, which is the most common material, but in our case, it is the choice of material that creates the performance. We want to pave the way for the industry with our research,” says Lars-Erik Wernersson.